[Linux-stm32] [PATCH] drm/stm: dsi: compute LP <=> HS time delay

Antonio Borneo antonio.borneo at foss.st.com
Mon May 31 15:48:45 UTC 2021


The driver uses a conservative set of hardcoded values for the
time delay between LP and HS, for either data and clock lanes.

By using the info in STM32MP15x datasheet, compute the actual
delay from lane's bps.
For the other devices whose datasheet don't provide this info yet,
stick to the legacy values.

Signed-off-by: Antonio Borneo <antonio.borneo at foss.st.com>
---
To: Philippe CORNU <philippe.cornu at foss.st.com>
To: Yannick Fertre <yannick.fertre at foss.st.com>
To: Raphael GALLAIS-POU <raphael.gallais-pou at foss.st.com>
Cc: linux-stm32 at st-md-mailman.stormreply.com

Ticket: https://intbugzilla.st.com/show_bug.cgi?id=91708

 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 8399d337589d..cd5054bb5bc1 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -309,10 +309,31 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
 	return 0;
 }
 
+#define DSI_PHY_DELAY(fp, vp, mbps) DIV_ROUND_UP((fp) * (mbps) + 1000 * (vp), 8000)
+
 static int
 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
 			   struct dw_mipi_dsi_dphy_timing *timing)
 {
+	struct dw_mipi_dsi_stm *dsi = priv_data;
+
+	if (dsi->hw_version == HWVER_131) {
+		/*
+		 * From datasheet of STM32MP15x
+		 * phy_clkhs2lp_time = (232+136*UI)/(8*UI)
+		 * phy_clklp2hs_time = (512+40*UI)/(8*UI)
+		 * phy_hs2lp_time = (128+64*UI)/(8*UI)
+		 * phy_lp2hs_time = (256+32*UI)/(8*UI)
+		 */
+		timing->clk_hs2lp = DSI_PHY_DELAY(232, 136, lane_mbps);
+		timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps);
+		timing->data_hs2lp = DSI_PHY_DELAY(128, 64, lane_mbps);
+		timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps);
+
+		return 0;
+	}
+
+	/* No data for the older DSI, yet */
 	timing->clk_hs2lp = 0x40;
 	timing->clk_lp2hs = 0x40;
 	timing->data_hs2lp = 0x40;
-- 
2.31.1




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