[Linux-stm32] STM32MP1 level triggered interrupts

[Marek Vasut]

On 1/24/20 10:17 AM, Alexandre Torgue wrote:
[...]
>>>>> Doing this kind of tricks in 2020 is pretty poor for a modern SoC.
>>>>
>>>> With the above assumption given, I think that is ok even in 2020.
>>>> (But I
>>>> wonder about SoCs in 2020 not being able to handle level sensitive irqs
>>>> :-)
>>>
>>> Quite. Seems incredibly restrictive, and very unfortunate.
>>
>> So I wonder, the EXTI should be able to read the GPIO line which caused
>> the interrupt when the interrupt handler returns, and trigger the
>> interrupt again if the line is still low. This might need some phandle
>> from the EXTI to GPIO bank in DT, but should be generally doable, no ?
>> It's a crutch all right.
>>
>> But I still wonder, what is the purpose of the EXTImux in that SoC?
>> Shouldn't that permit routing GPIOs directly into GIC SPIs, which would
>> then permit detecting at least level-high interrupts ?
>>
> 
> For this SoC, EXTI block detects external line edges and rises a GIC SPI
> interrupt. This EXTi block is mainly used to handle HW events like
> buttons, clocks ... So first issue seems more to be a design issue (your
> design doesn't fit with MP1 datasheet).

I am asking about the EXTImux block, see the DM00327659 datasheet
section 24.2 EXTI block diagram , figure 140 and exti[15:0] . Maybe that
permits routing external events directly to GIC SPIs ?

> Now, let's find a solution. I'll have a look on your proposition: "check
> the line in EOI callback and retrig".

That could probably work.

> Marc, this kind a solution could be acceptable on your side ?
> 
> regards
> Alex
> 
> 
> 
> 
> 


-- 
Best regards,
Marek Vasut