[Linux-stm32] [PATCH] ARM: dts: stm32: Add DH Electronics DHCOM SoM and PDK2 board

[Alexandre Torgue]

Hi Marek

Minor comments below.

On 1/17/20 1:51 PM, Marek Vasut wrote:
> On 1/15/20 5:46 PM, Patrick DELAUNAY wrote:
>> Hi Marek;
> 
> Hi,
> 
>> Adds the Linux Maintainers for STM32M linux patch:
> 
> Added, if there is a need for V2.
> 
> (no further comments below)
> 
> [...]
>>
>> Hi Alexandre,
>>
>> Can you review this patch.
>>
>> Regards
>>
>> Patrick
>>
>>> -----Original Message-----
>>> From: Marek Vasut <marex at denx.de>
>>> Sent: mercredi 15 janvier 2020 10:47
>>> To: linux-arm-kernel at lists.infradead.org
>>> Cc: Marek Vasut <marex at denx.de>; Patrick DELAUNAY
>>> <patrick.delaunay at st.com>; Patrice CHOTARD <patrice.chotard at st.com>
>>> Subject: [PATCH] ARM: dts: stm32: Add DH Electronics DHCOM SoM and PDK2
>>> board
>>> Importance: High
>>>
>>> Add support for DH Electronics DHCOM SoM and PDK2 rev. 400 carrier board.
>>> This is an SoM with STM32MP157C and an evaluation kit. The baseboard
>>> provides Ethernet, UART, USB, CAN and optional display.
>>>
>>> Signed-off-by: Marek Vasut <marex at denx.de>
>>> Cc: Patrick Delaunay <patrick.delaunay at st.com>
>>> Cc: Patrice Chotard <patrice.chotard at st.com>
>>> ---
>>>   arch/arm/boot/dts/Makefile                   |   1 +
>>>   arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts | 351 ++++++++++++++++++
>>> arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi | 368 +++++++++++++++++++
>>>   3 files changed, 720 insertions(+)
>>>   create mode 100644 arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts
>>>   create mode 100644 arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi
>>>

...

>>> +
>>> +&m_can1 {
>>> +	pinctrl-names = "default", "sleep";
>>> +	pinctrl-0 = <&m_can1_pins_a>;
>>> +	pinctrl-1 = <&m_can1_sleep_pins_a>;
>>> +	status = "okay";
>>> +};
>>> +
>>> +&pinctrl {

You could define DH pinctrl addons in stm32mp15-pinctrl.dtsi

>>> +	ethernet0_rmii_pins_a: rmii-0 {
>>> +		pins1 {
>>> +			pinmux = <STM32_PINMUX('G', 13, AF11)>, /*
>>> ETH1_RMII_TXD0 */
>>> +				 <STM32_PINMUX('G', 14, AF11)>, /*
>>> ETH1_RMII_TXD1 */
>>> +				 <STM32_PINMUX('B', 11, AF11)>, /*
>>> ETH1_RMII_TX_EN */
>>> +				 <STM32_PINMUX('A', 1, AF0)>,   /*
>>> ETH1_RMII_REF_CLK */
>>> +				 <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO
>>> */
>>> +				 <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC
>>> */
>>> +			bias-disable;
>>> +			drive-push-pull;
>>> +			slew-rate = <2>;
>>> +		};
>>> +		pins2 {
>>> +			pinmux = <STM32_PINMUX('C', 4, AF11)>,  /*
>>> ETH1_RMII_RXD0 */
>>> +				 <STM32_PINMUX('C', 5, AF11)>,  /*
>>> ETH1_RMII_RXD1 */
>>> +				 <STM32_PINMUX('A', 7, AF11)>;  /*
>>> ETH1_RMII_CRS_DV */
>>> +			bias-disable;
>>> +		};
>>> +	};
>>> +
>>> +	ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
>>> +		pins1 {
>>> +			pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /*
>>> ETH1_RMII_TXD0 */
>>> +				 <STM32_PINMUX('G', 14, ANALOG)>, /*
>>> ETH1_RMII_TXD1 */
>>> +				 <STM32_PINMUX('B', 11, ANALOG)>, /*
>>> ETH1_RMII_TX_EN */
>>> +				 <STM32_PINMUX('A', 2, ANALOG)>,  /*
>>> ETH1_MDIO */
>>> +				 <STM32_PINMUX('C', 1, ANALOG)>,  /*
>>> ETH1_MDC */
>>> +				 <STM32_PINMUX('C', 4, ANALOG)>,  /*
>>> ETH1_RMII_RXD0 */
>>> +				 <STM32_PINMUX('C', 5, ANALOG)>,  /*
>>> ETH1_RMII_RXD1 */
>>> +				 <STM32_PINMUX('A', 1, ANALOG)>,  /*
>>> ETH1_RMII_REF_CLK */
>>> +				 <STM32_PINMUX('A', 7, ANALOG)>;  /*
>>> ETH1_RMII_CRS_DV */
>>> +		};
>>> +	};
>>> +
>>> +	sai2_pins_a: sai2-0 {
>>> +		pins1 {
>>> +			pinmux = <STM32_PINMUX('I', 6, AF10)>,	/*
>>> SAI2_SD_A */
>>> +				 <STM32_PINMUX('I', 7, AF10)>,	/*
>>> SAI2_FS_A */
>>> +				 <STM32_PINMUX('D', 13, AF10)>;	/*
>>> SAI2_SCK_A */
>>> +			slew-rate = <0>;
>>> +			drive-push-pull;
>>> +			bias-disable;
>>> +		};
>>> +		pins2 {
>>> +			pinmux = <STM32_PINMUX('F', 11, AF10)>;	/*
>>> SAI2_SD_B */
>>> +			bias-disable;
>>> +		};
>>> +	};
>>> +
>>> +	sai2_sleep_pins_a: sai2-sleep-0 {
>>> +		pins {
>>> +			pinmux = <STM32_PINMUX('I', 6, ANALOG)>,  /*
>>> SAI2_SD_A */
>>> +				 <STM32_PINMUX('I', 7, ANALOG)>,  /*
>>> SAI2_FS_A */
>>> +				 <STM32_PINMUX('D', 13, ANALOG)>, /*
>>> SAI2_SCK_A */
>>> +				 <STM32_PINMUX('F', 11, ANALOG)>; /*
>>> SAI2_SD_B */
>>> +		};
>>> +	};
>>> +
>>> +	usart3_pins_a: usart3-0 {
>>> +		pins1 {
>>> +			pinmux = <STM32_PINMUX('B', 10, AF7)>; /*
>>> USART3_TX */
>>> +			bias-disable;
>>> +			drive-push-pull;
>>> +			slew-rate = <0>;
>>> +		};
>>> +		pins2 {
>>> +			pinmux = <STM32_PINMUX('B', 12, AF8)>; /*
>>> USART3_RX */
>>> +			bias-disable;
>>> +		};

...

>>> +&sdmmc3 {
>>> +	pinctrl-names = "default", "opendrain", "sleep";
>>> +	pinctrl-0 = <&sdmmc3_b4_pins_a>;
>>> +	pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
>>> +	pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
>>> +	broken-cd;
>>> +	st,neg-edge;
>>> +	bus-width = <4>;
>>> +	vmmc-supply = <&v3v3>;
>>> +	vqmmc-supply = <&v3v3>;
>>> +	mmc-ddr-3_3v;
>>> +	status = "okay";
>>> +};
>>> +
>>> +&qspi {

If you follow alphabetic order reorder this node.

>>> +	pinctrl-names = "default", "sleep";
>>> +	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
>>> +	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a
>>> &qspi_bk2_sleep_pins_a>;
>>> +	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
>>> +	#address-cells = <1>;
>>> +	#size-cells = <0>;
>>> +	status = "okay";
>>> +
>>> +	flash0: mx66l51235l at 0 {
>>> +		compatible = "jedec,spi-nor";
>>> +		reg = <0>;
>>> +		spi-rx-bus-width = <4>;
>>> +		spi-max-frequency = <108000000>;
>>> +		#address-cells = <1>;
>>> +		#size-cells = <1>;
>>> +	};
>>> +};
>>> +
>>> +&uart4 {
>>> +	pinctrl-names = "default";
>>> +	pinctrl-0 = <&uart4_pins_a>;
>>> +	status = "okay";
>>> +};
>>> --
>>> 2.24.1
>>
> 
>