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<div class="moz-cite-prefix">On 11/24/22 05:39, Sean Anderson wrote:<br>
</div>
<blockquote type="cite"
cite="mid:10afe73a-39f4-9aad-4501-fec9beb2fcd8@gmail.com">
<table class="moz-header-part1 moz-main-header" width="100%"
cellspacing="0" cellpadding="0" border="0">
<tbody>
<tr>
<td>
<div class="moz-header-display-name"
style="display:inline;">Subject: </div>
Re: [PATCH v3 1/3] dt-bindings: stm32mp13: add clock &
reset support for STM32MP13</td>
</tr>
<tr>
<td>
<div class="moz-header-display-name"
style="display:inline;">From: </div>
Sean Anderson <a class="moz-txt-link-rfc2396E" href="mailto:seanga2@gmail.com"><seanga2@gmail.com></a></td>
</tr>
<tr>
<td>
<div class="moz-header-display-name"
style="display:inline;">Date: </div>
11/24/22, 05:39</td>
</tr>
</tbody>
</table>
<table class="moz-header-part2 moz-main-header" width="100%"
cellspacing="0" cellpadding="0" border="0">
<tbody>
<tr>
<td>
<div class="moz-header-display-name"
style="display:inline;">To: </div>
Gabriel Fernandez <a class="moz-txt-link-rfc2396E" href="mailto:gabriel.fernandez@foss.st.com"><gabriel.fernandez@foss.st.com></a>,
<a class="moz-txt-link-abbreviated" href="mailto:u-boot@lists.denx.de">u-boot@lists.denx.de</a></td>
</tr>
<tr>
<td>
<div class="moz-header-display-name"
style="display:inline;">CC: </div>
Patrick DELAUNAY <a class="moz-txt-link-rfc2396E" href="mailto:patrick.delaunay@foss.st.com"><patrick.delaunay@foss.st.com></a>,
U-Boot STM32
<a class="moz-txt-link-rfc2396E" href="mailto:uboot-stm32@st-md-mailman.stormreply.com"><uboot-stm32@st-md-mailman.stormreply.com></a>, Patrice
Chotard <a class="moz-txt-link-rfc2396E" href="mailto:patrice.chotard@foss.st.com"><patrice.chotard@foss.st.com></a></td>
</tr>
</tbody>
</table>
<br>
<div class="moz-text-flowed" style="font-family: -moz-fixed;
font-size: 12px;" lang="x-unicode">On 11/22/22 03:05, Gabriel
Fernandez wrote:
<br>
<blockquote type="cite" style="color: #007cff;">Add support of
stm32mp13 DT bindings of clock and reset.
<br>
<br>
Signed-off-by: Gabriel Fernandez <a
class="moz-txt-link-rfc2396E"
href="mailto:gabriel.fernandez@foss.st.com"
moz-do-not-send="true"><gabriel.fernandez@foss.st.com></a>
<br>
Reviewed-by: Patrick Delaunay <a
class="moz-txt-link-rfc2396E"
href="mailto:patrick.delaunay@foss.st.com"
moz-do-not-send="true"><patrick.delaunay@foss.st.com></a>
<br>
---
<br>
<br>
(no changes since v1)
<br>
<br>
MAINTAINERS | 2 +
<br>
include/dt-bindings/clock/stm32mp13-clks.h | 229
+++++++++++++++++++
<br>
include/dt-bindings/reset/stm32mp13-resets.h | 100 ++++++++
<br>
3 files changed, 331 insertions(+)
<br>
create mode 100644
include/dt-bindings/clock/stm32mp13-clks.h
<br>
create mode 100644
include/dt-bindings/reset/stm32mp13-resets.h
<br>
<br>
diff --git a/MAINTAINERS b/MAINTAINERS
<br>
index 97b2f69f65..af2b835937 100644
<br>
--- a/MAINTAINERS
<br>
+++ b/MAINTAINERS
<br>
@@ -562,9 +562,11 @@ F: drivers/video/stm32/stm32_ltdc.c
<br>
F: drivers/watchdog/stm32mp_wdt.c
<br>
F: include/dt-bindings/clock/stm32fx-clock.h
<br>
F: include/dt-bindings/clock/stm32mp1-clks.h
<br>
+F: include/dt-bindings/clock/stm32mp13-clks.h
<br>
F: include/dt-bindings/clock/stm32mp1-clksrc.h
<br>
</blockquote>
<br>
Can we combine these? e.g.
<br>
<br>
F: include/dt-bindings/clock/stm32mp*
<br>
F: include/dt-bindings/reset/stm32mp*
<br>
</div>
</blockquote>
i preferred this one<br>
<blockquote type="cite"
cite="mid:10afe73a-39f4-9aad-4501-fec9beb2fcd8@gmail.com">
<div class="moz-text-flowed" style="font-family: -moz-fixed;
font-size: 12px;" lang="x-unicode">
<br>
Or even
<br>
<br>
F: include/dt-bindings/*/stm32mp*
<br>
<br>
--Sean
<br>
<br>
<blockquote type="cite" style="color: #007cff;"> F:
include/dt-bindings/pinctrl/stm32-pinfunc.h
<br>
F: include/dt-bindings/reset/stm32mp1-resets.h
<br>
+F: include/dt-bindings/reset/stm32mp13-resets.h
<br>
F: include/stm32_rcc.h
<br>
F: tools/stm32image.c
<br>
N: stm
<br>
</blockquote>
<br>
<br>
<blockquote type="cite" style="color: #007cff;">diff --git
a/include/dt-bindings/clock/stm32mp13-clks.h
b/include/dt-bindings/clock/stm32mp13-clks.h
<br>
new file mode 100644
<br>
index 0000000000..799dee5b80
<br>
--- /dev/null
<br>
+++ b/include/dt-bindings/clock/stm32mp13-clks.h
<br>
@@ -0,0 +1,229 @@
<br>
+/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause
*/
<br>
+/*
<br>
+ * Copyright (C) STMicroelectronics 2022 - All Rights
Reserved
<br>
+ * Author: Gabriel Fernandez <a
class="moz-txt-link-rfc2396E"
href="mailto:gabriel.fernandez@foss.st.com"
moz-do-not-send="true"><gabriel.fernandez@foss.st.com></a>
for STMicroelectronics.
<br>
+ */
<br>
+
<br>
+#ifndef <span class="moz-txt-underscore"><span
class="moz-txt-tag">_</span>DT_BINDINGS_STM32MP13_CLKS_H<span
class="moz-txt-tag">_</span></span>
<br>
+#define <span class="moz-txt-underscore"><span
class="moz-txt-tag">_</span>DT_BINDINGS_STM32MP13_CLKS_H<span
class="moz-txt-tag">_</span></span>
<br>
+
<br>
+/* OSCILLATOR clocks */
<br>
+#define CK_HSE 0
<br>
+#define CK_CSI 1
<br>
+#define CK_LSI 2
<br>
+#define CK_LSE 3
<br>
+#define CK_HSI 4
<br>
+#define CK_HSE_DIV2 5
<br>
+
<br>
+/* PLL */
<br>
+#define PLL1 6
<br>
+#define PLL2 7
<br>
+#define PLL3 8
<br>
+#define PLL4 9
<br>
+
<br>
+/* ODF */
<br>
+#define PLL1_P 10
<br>
+#define PLL1_Q 11
<br>
+#define PLL1_R 12
<br>
+#define PLL2_P 13
<br>
+#define PLL2_Q 14
<br>
+#define PLL2_R 15
<br>
+#define PLL3_P 16
<br>
+#define PLL3_Q 17
<br>
+#define PLL3_R 18
<br>
+#define PLL4_P 19
<br>
+#define PLL4_Q 20
<br>
+#define PLL4_R 21
<br>
+
<br>
+#define PCLK1 22
<br>
+#define PCLK2 23
<br>
+#define PCLK3 24
<br>
+#define PCLK4 25
<br>
+#define PCLK5 26
<br>
+#define PCLK6 27
<br>
+
<br>
+/* SYSTEM CLOCK */
<br>
+#define CK_PER 28
<br>
+#define CK_MPU 29
<br>
+#define CK_AXI 30
<br>
+#define CK_MLAHB 31
<br>
+
<br>
+/* BASE TIMER */
<br>
+#define CK_TIMG1 32
<br>
+#define CK_TIMG2 33
<br>
+#define CK_TIMG3 34
<br>
+
<br>
+/* AUX */
<br>
+#define RTC 35
<br>
+
<br>
+/* TRACE & DEBUG clocks */
<br>
+#define CK_DBG 36
<br>
+#define CK_TRACE 37
<br>
+
<br>
+/* MCO clocks */
<br>
+#define CK_MCO1 38
<br>
+#define CK_MCO2 39
<br>
+
<br>
+/* IP clocks */
<br>
+#define SYSCFG 40
<br>
+#define VREF 41
<br>
+#define DTS 42
<br>
+#define PMBCTRL 43
<br>
+#define HDP 44
<br>
+#define IWDG2 45
<br>
+#define STGENRO 46
<br>
+#define USART1 47
<br>
+#define RTCAPB 48
<br>
+#define TZC 49
<br>
+#define TZPC 50
<br>
+#define IWDG1 51
<br>
+#define BSEC 52
<br>
+#define DMA1 53
<br>
+#define DMA2 54
<br>
+#define DMAMUX1 55
<br>
+#define DMAMUX2 56
<br>
+#define GPIOA 57
<br>
+#define GPIOB 58
<br>
+#define GPIOC 59
<br>
+#define GPIOD 60
<br>
+#define GPIOE 61
<br>
+#define GPIOF 62
<br>
+#define GPIOG 63
<br>
+#define GPIOH 64
<br>
+#define GPIOI 65
<br>
+#define CRYP1 66
<br>
+#define HASH1 67
<br>
+#define BKPSRAM 68
<br>
+#define MDMA 69
<br>
+#define CRC1 70
<br>
+#define USBH 71
<br>
+#define DMA3 72
<br>
+#define TSC 73
<br>
+#define PKA 74
<br>
+#define AXIMC 75
<br>
+#define MCE 76
<br>
+#define ETH1TX 77
<br>
+#define ETH2TX 78
<br>
+#define ETH1RX 79
<br>
+#define ETH2RX 80
<br>
+#define ETH1MAC 81
<br>
+#define ETH2MAC 82
<br>
+#define ETH1STP 83
<br>
+#define ETH2STP 84
<br>
+
<br>
+/* IP clocks with parents */
<br>
+#define SDMMC1_K 85
<br>
+#define SDMMC2_K 86
<br>
+#define ADC1_K 87
<br>
+#define ADC2_K 88
<br>
+#define FMC_K 89
<br>
+#define QSPI_K 90
<br>
+#define RNG1_K 91
<br>
+#define USBPHY_K 92
<br>
+#define STGEN_K 93
<br>
+#define SPDIF_K 94
<br>
+#define SPI1_K 95
<br>
+#define SPI2_K 96
<br>
+#define SPI3_K 97
<br>
+#define SPI4_K 98
<br>
+#define SPI5_K 99
<br>
+#define I2C1_K 100
<br>
+#define I2C2_K 101
<br>
+#define I2C3_K 102
<br>
+#define I2C4_K 103
<br>
+#define I2C5_K 104
<br>
+#define TIM2_K 105
<br>
+#define TIM3_K 106
<br>
+#define TIM4_K 107
<br>
+#define TIM5_K 108
<br>
+#define TIM6_K 109
<br>
+#define TIM7_K 110
<br>
+#define TIM12_K 111
<br>
+#define TIM13_K 112
<br>
+#define TIM14_K 113
<br>
+#define TIM1_K 114
<br>
+#define TIM8_K 115
<br>
+#define TIM15_K 116
<br>
+#define TIM16_K 117
<br>
+#define TIM17_K 118
<br>
+#define LPTIM1_K 119
<br>
+#define LPTIM2_K 120
<br>
+#define LPTIM3_K 121
<br>
+#define LPTIM4_K 122
<br>
+#define LPTIM5_K 123
<br>
+#define USART1_K 124
<br>
+#define USART2_K 125
<br>
+#define USART3_K 126
<br>
+#define UART4_K 127
<br>
+#define UART5_K 128
<br>
+#define USART6_K 129
<br>
+#define UART7_K 130
<br>
+#define UART8_K 131
<br>
+#define DFSDM_K 132
<br>
+#define FDCAN_K 133
<br>
+#define SAI1_K 134
<br>
+#define SAI2_K 135
<br>
+#define ADFSDM_K 136
<br>
+#define USBO_K 137
<br>
+#define LTDC_PX 138
<br>
+#define ETH1CK_K 139
<br>
+#define ETH1PTP_K 140
<br>
+#define ETH2CK_K 141
<br>
+#define ETH2PTP_K 142
<br>
+#define DCMIPP_K 143
<br>
+#define SAES_K 144
<br>
+#define DTS_K 145
<br>
+
<br>
+/* DDR */
<br>
+#define DDRC1 146
<br>
+#define DDRC1LP 147
<br>
+#define DDRC2 148
<br>
+#define DDRC2LP 149
<br>
+#define DDRPHYC 150
<br>
+#define DDRPHYCLP 151
<br>
+#define DDRCAPB 152
<br>
+#define DDRCAPBLP 153
<br>
+#define AXIDCG 154
<br>
+#define DDRPHYCAPB 155
<br>
+#define DDRPHYCAPBLP 156
<br>
+#define DDRPERFM 157
<br>
+
<br>
+#define ADC1 158
<br>
+#define ADC2 159
<br>
+#define SAI1 160
<br>
+#define SAI2 161
<br>
+
<br>
+#define STM32MP1_LAST_CLK 162
<br>
+
<br>
+/* SCMI clock identifiers */
<br>
+#define CK_SCMI_HSE 0
<br>
+#define CK_SCMI_HSI 1
<br>
+#define CK_SCMI_CSI 2
<br>
+#define CK_SCMI_LSE 3
<br>
+#define CK_SCMI_LSI 4
<br>
+#define CK_SCMI_HSE_DIV2 5
<br>
+#define CK_SCMI_PLL2_Q 6
<br>
+#define CK_SCMI_PLL2_R 7
<br>
+#define CK_SCMI_PLL3_P 8
<br>
+#define CK_SCMI_PLL3_Q 9
<br>
+#define CK_SCMI_PLL3_R 10
<br>
+#define CK_SCMI_PLL4_P 11
<br>
+#define CK_SCMI_PLL4_Q 12
<br>
+#define CK_SCMI_PLL4_R 13
<br>
+#define CK_SCMI_MPU 14
<br>
+#define CK_SCMI_AXI 15
<br>
+#define CK_SCMI_MLAHB 16
<br>
+#define CK_SCMI_CKPER 17
<br>
+#define CK_SCMI_PCLK1 18
<br>
+#define CK_SCMI_PCLK2 19
<br>
+#define CK_SCMI_PCLK3 20
<br>
+#define CK_SCMI_PCLK4 21
<br>
+#define CK_SCMI_PCLK5 22
<br>
+#define CK_SCMI_PCLK6 23
<br>
+#define CK_SCMI_CKTIMG1 24
<br>
+#define CK_SCMI_CKTIMG2 25
<br>
+#define CK_SCMI_CKTIMG3 26
<br>
+#define CK_SCMI_RTC 27
<br>
+#define CK_SCMI_RTCAPB 28
<br>
+
<br>
+#endif /* <span class="moz-txt-underscore"><span
class="moz-txt-tag">_</span>DT_BINDINGS_STM32MP13_CLKS_H<span
class="moz-txt-tag">_</span></span> */
<br>
diff --git a/include/dt-bindings/reset/stm32mp13-resets.h
b/include/dt-bindings/reset/stm32mp13-resets.h
<br>
new file mode 100644
<br>
index 0000000000..18ccb05db6
<br>
--- /dev/null
<br>
+++ b/include/dt-bindings/reset/stm32mp13-resets.h
<br>
@@ -0,0 +1,100 @@
<br>
+/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause
*/
<br>
+/*
<br>
+ * Copyright (C) STMicroelectronics 2022 - All Rights
Reserved
<br>
+ * Author: Gabriel Fernandez <a
class="moz-txt-link-rfc2396E"
href="mailto:gabriel.fernandez@foss.st.com"
moz-do-not-send="true"><gabriel.fernandez@foss.st.com></a>
for STMicroelectronics.
<br>
+ */
<br>
+
<br>
+#ifndef <span class="moz-txt-underscore"><span
class="moz-txt-tag">_</span>DT_BINDINGS_STM32MP13_RESET_H<span
class="moz-txt-tag">_</span></span>
<br>
+#define <span class="moz-txt-underscore"><span
class="moz-txt-tag">_</span>DT_BINDINGS_STM32MP13_RESET_H<span
class="moz-txt-tag">_</span></span>
<br>
+
<br>
+#define TIM2_R 13568
<br>
+#define TIM3_R 13569
<br>
+#define TIM4_R 13570
<br>
+#define TIM5_R 13571
<br>
+#define TIM6_R 13572
<br>
+#define TIM7_R 13573
<br>
+#define LPTIM1_R 13577
<br>
+#define SPI2_R 13579
<br>
+#define SPI3_R 13580
<br>
+#define USART3_R 13583
<br>
+#define UART4_R 13584
<br>
+#define UART5_R 13585
<br>
+#define UART7_R 13586
<br>
+#define UART8_R 13587
<br>
+#define I2C1_R 13589
<br>
+#define I2C2_R 13590
<br>
+#define SPDIF_R 13594
<br>
+#define TIM1_R 13632
<br>
+#define TIM8_R 13633
<br>
+#define SPI1_R 13640
<br>
+#define USART6_R 13645
<br>
+#define SAI1_R 13648
<br>
+#define SAI2_R 13649
<br>
+#define DFSDM_R 13652
<br>
+#define FDCAN_R 13656
<br>
+#define LPTIM2_R 13696
<br>
+#define LPTIM3_R 13697
<br>
+#define LPTIM4_R 13698
<br>
+#define LPTIM5_R 13699
<br>
+#define SYSCFG_R 13707
<br>
+#define VREF_R 13709
<br>
+#define DTS_R 13712
<br>
+#define PMBCTRL_R 13713
<br>
+#define LTDC_R 13760
<br>
+#define DCMIPP_R 13761
<br>
+#define DDRPERFM_R 13768
<br>
+#define USBPHY_R 13776
<br>
+#define STGEN_R 13844
<br>
+#define USART1_R 13888
<br>
+#define USART2_R 13889
<br>
+#define SPI4_R 13890
<br>
+#define SPI5_R 13891
<br>
+#define I2C3_R 13892
<br>
+#define I2C4_R 13893
<br>
+#define I2C5_R 13894
<br>
+#define TIM12_R 13895
<br>
+#define TIM13_R 13896
<br>
+#define TIM14_R 13897
<br>
+#define TIM15_R 13898
<br>
+#define TIM16_R 13899
<br>
+#define TIM17_R 13900
<br>
+#define DMA1_R 13952
<br>
+#define DMA2_R 13953
<br>
+#define DMAMUX1_R 13954
<br>
+#define DMA3_R 13955
<br>
+#define DMAMUX2_R 13956
<br>
+#define ADC1_R 13957
<br>
+#define ADC2_R 13958
<br>
+#define USBO_R 13960
<br>
+#define GPIOA_R 14080
<br>
+#define GPIOB_R 14081
<br>
+#define GPIOC_R 14082
<br>
+#define GPIOD_R 14083
<br>
+#define GPIOE_R 14084
<br>
+#define GPIOF_R 14085
<br>
+#define GPIOG_R 14086
<br>
+#define GPIOH_R 14087
<br>
+#define GPIOI_R 14088
<br>
+#define TSC_R 14095
<br>
+#define PKA_R 14146
<br>
+#define SAES_R 14147
<br>
+#define CRYP1_R 14148
<br>
+#define HASH1_R 14149
<br>
+#define RNG1_R 14150
<br>
+#define AXIMC_R 14160
<br>
+#define MDMA_R 14208
<br>
+#define MCE_R 14209
<br>
+#define ETH1MAC_R 14218
<br>
+#define FMC_R 14220
<br>
+#define QSPI_R 14222
<br>
+#define SDMMC1_R 14224
<br>
+#define SDMMC2_R 14225
<br>
+#define CRC1_R 14228
<br>
+#define USBH_R 14232
<br>
+#define ETH2MAC_R 14238
<br>
+
<br>
+/* SCMI reset domain identifiers */
<br>
+#define RST_SCMI_LTDC 0
<br>
+#define RST_SCMI_MDMA 1
<br>
+
<br>
+#endif /* <span class="moz-txt-underscore"><span
class="moz-txt-tag">_</span>DT_BINDINGS_STM32MP13_RESET_H<span
class="moz-txt-tag">_</span></span> */
<br>
</blockquote>
<br>
</div>
</blockquote>
</body>
</html>